In serializer/deserializer (SERDES) circuits, a differential signaling scheme commonly referred to as current mode logic (CML) may be used for clock distribution in a device. A typical CML driver may receive an input differential clock signal and provide an output differential clock signal to a variety of components, such as a transmit circuit or receive circuit of the device.
CML drivers typically operate within predetermined frequency ranges. Because different devices may have different data rates and/or different clock speeds, a given CML driver may be less suitable for some devices than for other devices. Thus, it is desirable for the given CML driver to be suitable for a wide range of devices operating over a wide range of data rates and/or clock speeds.